EverTest can automatically isolate any Simulink subsystem from the remainder of the model and create a test harness which provides:

• time sequences of input data to stimulate the unit
• parameter values to test variants of functionality
• expected output data for the reference behavior
• an assessment mechanism to verify the unit behavior

EverTest provides a graphical user interface (GUI) to interact with the test object and the test case specification.

The GUI can be accessed by double-clicking on the EverTest blocks inside the test harness model. The toolbar contains the controls for the test configuration, the test specification and the work-product management. From the toolbar you can access product help where all the features are explained in detail.

In the EverTest specification you can define which inputs, outputs and parameters will be used during simulation. The Interface specification for signals and parameters includes the following characteristics: Name, Type, Data Type, Dimension, Min, Max, Unit and Description.

In the Interface sheet you can define all the interface characteristics including port order. The CleanUp-Function propagates the modifications to selected test-cases and sets the order, colors and other formal data properties for all selected test-cases.

EverTest automatically creates the Simulink.Parameter objects with the predefined properties. You can redefine the parameter values for each test-case.

EverTest automates the following assessment actions for each test case:

• The outputs are permanently stored.
• The outputs are compared to references.
• The comparison results are visualized.
• All test results are summarized in a textual form.

The green color indicates a passed assessment.The light-green color means that the test case passed within tolerances. The red color is used when the output value is other than expected, i.e. the test case has failed.

Two types of tolerance ranges are supported: the absolute and the relative tolerances. Both tolerance types can be combined for more flexibility. The tolerance ranges can be used asymmetrically.

To support the impact analysis and assessments all requirements shall be traceable referencing to each source of the requirement, each realization in the design, and each specification of its verification.

The EverTest Requirements-Traceability-Matrix provides answers to the following questions:

• Where are the requirements implemented?
• Where are the requirements verified?
• What are the verification results?

The red color means that the Requirement-ID was found in the model but it is missing in the verification specification, so there is no evidence of requirements-based verification.

The yellow color means that the Requirement-ID was found in the verification specification but it is missing in the model, so the traceability has yet to be achieved in the model.

The green color is used when the Requirement-ID was found in both the model and the verification specification, so we can assume that the requirements-based test was conducted. The formal inspection of the test-case shall be triggered.

The Matrix helps linking requirements to the corresponding design elements, code and test cases. Specifying such requirements references takes little effort during development but is the most impotent characteristic of the excellent software.

For testing, the specification of each test case shall include the input data, their time sequence and their values.

To model simple sequences of test steps like f.e. signal vectors, parameter settings or signal ramping, the direct test-case definition can be used. It is a very fast way of test signal generation which is easy to document and easy to review.

The more complicated test sequences can be generated in Simulink. You can reconfigure the EverTest interface specification from “Type-I” (for Input) to “Type-Ic” (for Input for Close-Loop Simulation).

Such interface specification adds an extra input to the EverTest_Source-block to feedthrough and document any signal from the Simulink model. Now you can use different Simulink source blocks for importing measurement data and for defining signals as a function of time.

Different modelling methods can be combined allowing generation of test sequences with arbitrary complexity. Such test sequences will be saved in a test-case specification for documentation, analysis and debugging. The imported signals are grayed out to demonstrate that they are provided from an external source.

You can now reconfigure the EverTest interface specification “Type-Ic” (for Input for Close-Loop Simulation) to “Type-Io” (for Input for Open-Loop Simulation) to deterministically reuse or manually modify the recorded data. The inport of EverTest_Source-block will not be deleted in order to preserve the signal line connection.

However you can switch to the regular “Type-I” interface to delete the inport if needed.

The EverTest software can be used to create and run test cases and monitor the behaviour of the test objects with base line assessments, i.e. direct comparison of real and expected values.

The EverTest software documents the input data, their time sequence, and the expected behaviour which includes output data, acceptable ranges of output values, time behaviour and tolerance behaviour.

The base line assessments can be combined with more complex assessments modelled in MATLAB, Simulink and Stateflow, which is more effective than in other external tools or programming languages.

The assessment models can combine conditional comparisons of outputs, monitoring of interface ranges, analysis of state sequence order and restrictions on time behaviour.

Such test assessments are particularly effective at reducing the size of test suites for very complex applications, making testing more targeted and efficient. Please open the web view of the model to inspect an example test assessment implementation.

They can be verified in the same verification cycle and with the same verification tools as the test objects.

Please note that the regular base-line assessments are still a better choice for simple applications at the unit level as they are much faster and easier in development and maintenance.

EverTest streamlines requirements-based verification with its documentation capability, which completes the model-based tool chain.

Graphical signal representation in a test report helps reviewing the test cases. Please use the EverPlot() function in the test case Description field to plot single bits of a bitfield, scalar values or vector signals. For more flexibility you can modify the test data by using the MATLAB notation. You also can specify the color, the line style and the line markes. The related time vector, reference and tolerance values for output signals will be plotted automatically, no need to pass them as arguments to the EverPlot() function. You may use parameters, constants and MATLAB functions as supportive horizontal lines.

You may show the comments on the plot by putting ‘>’ prior to the comment in the Description field. Vertical dotted lines along with comments will appear above the plot. You may zoom some area on the plot and come back to the original view. You can click on the signal legend to highlight particular signal in the plot and in the table below. You can hide the signal by switching them off in the legend.

You may generate multiple plots by using the function multiple times. The feature is helpful when dealing with signals of very different ranges, i.e. [0 1] versa [-100 9999].

The generated plots are interactive. You can analyze particular areas of the plot by using the value pointer which is synchronized for all data. The signal values are visible in the legend. The changing values are marked in red. You can zoom into some area.

You can filter out some signals in the table which you do not need for the analysis of the particular test case by using a !EverPlot function. The data is still present in the report which is indicated by the red tri-angle near the time vector. You can activate the data-display if needed.

Here is the automatically generated EverTest Report demonstrating the EverPlot function.

EverTest provides a one-click interface to utilize EverCheck software for static model analysis. EverTest triggers the model checker and then renames and relocates the automatically generated EverCheck Report based on project-specific settings.

EverCheck is a qualifiable tool for static model analysis of Simulink® and Stateflow® models and libraries. EverCheck provides all you need to check your models, including modelling quidelines, design fixes, verification reports and support.

EverCheck software enforces just enough process to help you deliver safety compliant applications, providing a safe subset of a modeling language, and detecting run-time and logic errors at any model development stage. EverCheck has been certified as a tool for static model verification within a qualified development environment under ISO 26262 safety standard. It supports any MATLAB release since R2012b. No product training is needed to become productive.

Key Features of EverCheck:

• Modeling guidelines for safety related applications
• Compliance checking for modeling guidelines
• Kontext-based exclusion handling and documentation
• Automated report-renaming and -relocation
• Automated guideline-based model correction
• Model-web-view generator with a search capability
• Qualification kit with validation tests
• Programmable scripting interface for check automation
• Best in class usability and performance

EverTest provides a one-click interface to utilize Simulink Coverage software which collects structural test coverage on model and code level for all executed test cases. Both decision coverage (branch coverage) and modified condition decision coverage (MCDC) are supported. EverTest provides intrinsic exclusion handling (see grayed out block in the picture below). EverTest merges all work products to a self-contained coverage report, renames and relocates it based on project-specific settings. Open model coverage report and review missing coverage information for red blocks in the model screenshot below. Open code coverage report to see how the findings on the model level correlate to those in the generated C code.

EverTest enables requirements-based, baseline, equivalence, and back-to-back testing, including software-in-the-loop (SIL) and processor-in-the-loop (PIL) for external C-Code.

By selecting the EverTest Debug Mode, you can start the simulation for selected test cases in a step-by-step debugger. The EverTest Buttons enable debugging control. The Information Bar displays the current time step.

With the EverTest step-by-step debugger you can:

• View outport values of all Simulink blocks for each time step
• View relevant signals on Simulink scopes and viewers
• View all previous and current output values in the test specification file
• Jump to a relevant time step by using the Continue Button

EverTest generates an ISO 26262-8 compliant verification report in HTML format. The report is self-contained, i.e. it consists of one single file to simplify version control. The report provides a summary of verification activities, the the information about the testing environment, test harness, test object and the results of dynamic tests in line with the test specification.

EverTest supports export and import of test cases for following data formats:

EverTest provides complete user documentation and a safety manual which was designed for unit testing at model level in the Simulink environment. The safety manual provides information needed by function developers to assist them in the unit verification of safety related applications at model level. Following the procedures described in the safety manual ensures correct usage of the EverTest software in order to comply with the safety standards.